current "done" projects on OpenCores

[Dave Long]

> There's a company, DRC, that sells a high-performance FPGA board that
> plugs into cpu sockets on multi-cpu motherboards:

That's another virtuous cycle: usually the problem with selling 
accelerator boards is that it normally just takes the problem of 
crunching some ops and turns it into the hassle of feeding the board 
with data and getting the results back.  Presumably the sockets on a 
multi-cpu motherboard are able to communicate in a way that looks much 
more like a coprocessor call than a DMA.

> I expect FPGAs to grow in popularity for general computing.  Perhaps
> some day every computer will have a CPU, RAM, FPGA, and IO.  Will
> programmers study circuit design or will they write code in high level
> languages that can be compiled to the FPGA?  I guess that it would be
> much easier to compile Haskell code to a circuit than C code.

There are several Haskell/FP hardware design languages.  (the only one 
that comes to mind immediately is "Ruby", which is probably far too old 
to be a good example, and is noteworthy mostly for the name collision 
with the software language)

I believe computing HW design is the converse of SW design in that:

- parallel pattern matching is easy, but
- sequential pattern matching (looping) is difficult

If you look at what Horowitz and Hill had to say about how the 
introduction of PLDs made hardware cleaner*, it has many parallels with 
the FP approach to software.  Basically, they liked PLDs because one 
could have inputs (and last register state) flow into the logic, and 
then take the outputs directly out of the registers, 
inputs->logic->registers->output, breaking up the customary feedback 
loop of inputs->logic->registers->logic->outputs and meaning that the 
register clock was synchronous: no longer several gate delays away from 
the ultimate outputs.  (timing and synchronization seem to be to 
hardware what memory and GC are to software)

 From a software point of view, a little ravioli of logic with some 
registers stuffed in the middle and wires going in all directions looks 
very much like an OO view of the world, while a system in which the 
information flow through the logic gates is in one direction, with the 
outputs (and state feedback) provided at a single well-defined place, 
looks much more like an FP view of the world, with IO and State being 
done in monads which are "run" at well defined places.

-Dave

* cf "FPGA end-user programmability: how to achieve?"
http://www.mail-archive.com/kragen-discuss@canonical.org/msg00194.html

also, Dan Piponi's embedded lazy FP led-proto:
http://sigfpe.blogspot.com/2006/06/monadic-lightswitch.html